Reading from files is very important for VHDL simulation. Apart from using it in self-designed testbenches, many commercially available testbench components make use of this method, too. This section will illustrate how to read file using VHDL 93 syntax.
Here is an example entity header:
entity FILE_READ is generic( stim_file: string :="sim.dat" ); port( CLK : in std_logic; RST : in std_logic; Y : out std_logic_vector(4 downto 0); EOG : out std_logic ); end FILE_READ;
In this example data is read from a file sim.dat at every rising clock edge and applied to the output vector Y. Once every line of the file is read the EOG (End Of Generation) flag is set.
The declaration of the input file is shown below:
architecture read_from_file of FILE_READ is file stimulus: TEXT open read_mode is stim_file; begin
The file is stimulus, it's of type TEXT and opened in read mode. The file name is defined in the string stim_file. (stim_file is a generic, defined in the entity header).
Just as a file write, a file read is done in two steps. The first step fetches a line from a file and stores it in a line type variable (readline command) the second reads a string from the line (read command):
EOG <= '0'; -- wait for Reset to complete wait until RST='1'; wait until RST='0'; while not endfile(stimulus) loop -- read digital data from input file readline(stimulus, l); read(l, s); Y <= to_std_logic_vector(s); wait until CLK = '1'; end loop; print("I@FILE_READ: reached end of "& stim_file); EOG <= '1'; wait;Since a string is read from the input file, a conversion function is required to obtain a std_logic_vector. The function to_std_logic_vector(s) achieves that, it is part of the txt_util package.
With the following contents of sim.dat:
00010 00011 11100 1UXZW HL111 11111
...file_read.vhd will generate these waveforms:
Below are the files which have been simulated in this section: